The BRAM-ring Bounty: The FPGA Stays Undefeated

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The BRAM-ring Bounty: The FPGA Stays Undefeated
The BRAM-ring Bounty: The FPGA Stays Undefeated1920×1080 174 KB

The BRAM-ring bounty, which opened on 6 October 2026, is now closed, and everyone who wanted to take part had a whole month to enter.

Nexa Chief Scientist Dr Peter Rizun announced the results: five valid entries and no one claiming the main 0.1 BTC bounty. However, the CPU kernel was improved, and a 0.01 BTC bounty was successfully claimed.

The BRAM-ring Bounty

The BRAM-ring bounty was announced on 6 October 2026 on Peter Rizun’s X account, attracting more than a quarter of a million views. The bounty closed on 4 November 2026, 23:59 Pacific time.

Peter designed a proof-of-work called BRAM-ring. A $40 Efinix Tz170 FPGA does 37,100 H/s on it, and anyone who could match that per dollar with non-FPGA hardware could claim the main bounty.

The bounty:

  • 0.1 BTC to the first person who shows non-FPGA hardware at or above 371 H/s per dollar

  • 0.01 BTC every time someone beats his GPU or CPU kernel by 10% (bit-exact, measured on his machine, the bar ratchets)

  • 0.01 BTC for a real shortcut in the function: half the work per hash, counted not timed

Five claims came in, every one of them bit-exact on all 8 vectors and on a fresh seed. That alone is a good sign for the spec, with five independent implementations and zero disagreements.

The Claims

Below is every claim in the announcement thread, in reply order, with what the reference machine measured:

Reply (Pacific) Entrant Prize Result
2026-10-19 @inkier35 CPU −2%, not awarded
2026-10-20 @sulla_alexander CPU −42%, not awarded
2026-10-21 @sulla_alexander GPU −39%, not awarded
2026-10-21 @sulla_alexander CPU −43%, not awarded
2026-11-03 @AlexnderSmith04 CPU +14%, awarded

  • @inkier35: unrolled gather chains, a 2% miss on the reference machine.

  • @sulla_alexander: three claims, scalar taps on CPU and a tiled-bank kernel on GPU. Big wins on their own hardware that didn’t transfer, and the Downfall lesson is now in the README for posterity.

All five were bit-exact, cleanly packaged and honestly reported as local results pending this measurement.

The Winner

The winner is @AlexnderSmith04 with Prefetch32: an algebraic-normal-form cell evaluator plus a 32-lane deferred read-modify-write, +14% over the shipped CPU kernel, measured back to back on the 12700KF. The decision is final, and the bounty reward is 0.01 BTC.

The ANF cell evaluator and the 32-lane deferred read-modify-write are the first changes to beat the shipped kernel on this machine. Prefetch32 is now the CPU champion at 932 H/s.

There were two changes, both aimed at the memory side. The first change hides latency the shipped kernel was eating, and the second shaves the compute that was left. Neither reduces the memory traffic, which is the point of the function: the moat shrank from 90× to 80×.

Standalone hash rates, each attack on its own silicon (i7-12700KF / 20 threads, RTX 3070, Efinix Ti375 devkit):

Competitor Hash rate Notes
CPU, naive, 20 threads 131 H/s one nonce per core, readable baseline
CPU champion: Prefetch32 (awarded 2026-11-03) 932 H/s ANF cell evaluator + 32-lane deferred RMW on top of our kernel
CPU, AVX2 lane-parallel, shipped kernel 822 H/s our strongest CPU attack
GPU, RTX 3070, best CUDA 1,493 H/s at the card’s measured scattered-RMW wall
FPGA, Ti375, 2 rings @ 95 MHz 74,233 H/s measured on silicon at full speed

That’s ~50× the GPU and ~80× the CPU champion (~90× our own kernel), measured kernel against measured silicon.

The Main Prize

Everything is judged by one number: mean hash rate per US dollar of hardware. The 0.1 BTC goes unclaimed. Nobody showed non-FPGA hardware within 100× of 371 H/s per dollar, and the best CPU result after a month of public attack is 932 H/s, against 37,100 from a $40 chip. The little FPGA stays undefeated.

Why It Matters for Nexa

NEXA BRAM-ring is a proof-of-work function tailored to run fast on a cheap FPGA and slow on CPUs and GPUs.

Logic is cheap, and so is memory. What’s scarce is random-access bandwidth between them: how many independent, data-dependent memory accesses a chip can serve every cycle. This function gives every nonce its own pile of small RAMs and reads and writes them at data-dependent addresses every step. An FPGA has hundreds of independent single-cycle RAM blocks, each with its own port, wired next to its logic, so it does this for free. A CPU or GPU has to fake those RAMs out of one shared memory system and chokes once it runs enough nonces in parallel to keep its ALUs busy.

To Wrap Up

The BRAM-ring bounty was announced publicly and was open for a whole month. During this time, we saw a few entries and one success in improving kernel efficiency. However, none of the entries even tried to beat the efficiency of the $40 FPGA chip. FPGAs are what Nexa is building on, for signature verification and for mining.

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